1. Field of the Invention
The present invention relates generally to selective epitaxy deposition of silicon-containing materials in semiconductor processing. More particularly, this application relates to selective epitaxy deposition of silicon-containing materials and substitutionally carbon-doped silicon-containing materials by using a modified chemical vapor deposition (mCVD) conditions using tetrasilane and a carbon source and an apparatus for accomplishing the same.
2. Description of the State of the Art
The relentless pursuit of scaling over the last 40 years, in accordance with the famed postulate known as Moore's Law, continues to be an aggressive goal. However, the time has come to rethink what is scalable and examine other ways of adding value to semiconductor devices. As smaller transistors are manufactured, ultra shallow source/drain junctions are becoming more challenging to produce. Generally, sub-100 nm CMOS (complementary metal-oxide semiconductor) devices require a junction depth to be less than 30 nm. Selective epitaxial deposition is often utilized to form epilayers of silicon-containing materials (e.g., Si, SiGe and SiC) into the junctions. Generally, selective epitaxial deposition permits growth of epilayers on silicon moats with no growth on dielectric areas. Selective epitaxy can be used within semiconductor devices, such as elevated source/drains, source/drain extensions, contact plugs or base layer deposition of bipolar devices.
Chemical vapor deposition (CVD) is a chemical process used to produce high-purity, high-performance solid materials. The process is often used in the semiconductor industry to produce thin films. In a typical CVD process, the wafer (substrate) is exposed to one or more volatile precursors, which react and/or decompose on the substrate surface to produce the desired deposit. Frequently, volatile by-products are also produced, which are removed by gas flow through the reaction chamber.
A number of forms of CVD are in wide use and are frequently referenced in the literature. These processes differ in the means by which chemical reactions are initiated (e.g., activation process) and process conditions. The following are but a few examples of CVD as classified by operating pressure:                Low-pressure CVD (LPCVD)—CVD processes at subatmospheric pressures (10−3 Torr base pressure/100 mTorr-1 Torr operating pressure).        Ultrahigh vacuum CVD (UHVCVD)—CVD processes at a very low pressure, typically 10−9 Torr base/10−5 to 50 mTorr operating pressure.        Reduced-Pressure CVD (RPCVD)—CVD process at 10−3 Torr base pressure/10 Torr to ATM operating pressure.        Very Low Pressure CVD (VLPCVD)—CVD process at 10−7 Torr base/10 mTorr to 50 mTorr operating pressure.        
Generally, a selective epitaxy process involves a deposition reaction and an etch reaction. The deposition and etch reactions occur simultaneously with relatively different reaction rates to an epitaxial layer and to a polycrystalline layer. During the deposition process, the epitaxial layer is formed on a monocrystalline surface while a polycrystalline layer is deposited on at least a second layer, such as an existing polycrystalline layer and/or an amorphous layer. However, the deposited polycrystalline layer is generally etched at a faster rate than the epitaxial layer. Therefore, by changing the concentration of an etchant gas, the net selective process results in deposition of epitaxy material and limited, or no, deposition of polycrystalline material. For example, a selective epitaxy process may result in the formation of an epilayer of silicon-containing material on a monocrystalline silicon surface while no deposition is left on the spacer.
Selective epitaxy deposition of silicon-containing materials has become a useful technique during formation of elevated source/drain and source/drain extension features, for example, during the formation of silicon-containing MOSFET (metal oxide semiconductor field effect transistor) devices. Source/drain extension features are manufactured by etching a silicon surface to make a recessed source/drain feature and subsequently filling the etched surface with a selectively grown epilayers, such as a silicon germanium (SiGe) material. Selective epitaxy permits near complete dopant activation with in situ doping, so that the post annealing process is omitted. Therefore, junction depth can be defined accurately by silicon etching and selective epitaxy. On the other hand, the ultra shallow source/drain junction inevitably results in increased series resistance. Also, junction consumption during silicide formation increases the series resistance even further. In order to compensate for junction consumption, an elevated source/drain is epitaxially and selectively grown on the junction. Typically, the elevated source/drain layer is undoped silicon.
However, current selective epitaxy processes have some drawbacks. In order to maintain selectivity during present epitaxy processes, chemical concentrations of the precursors, as well as reaction temperatures must be regulated and adjusted throughout the deposition process. If not enough silicon precursor is administered, then the etching reaction may dominate and the overall process is slowed down. If not enough etchant precursor is administered, then the deposition reaction may dominate reducing the selectivity to form monocrystalline and polycrystalline materials across the substrate surface. Also, current selective epitaxy processes usually require a high reaction temperature, such as about 800° C., 1,000° C. or higher. Such high temperatures are not desirable during a fabrication process due to thermal budget considerations and possible uncontrolled nitridation reactions to the substrate surface.
The performance of semiconductors devices may be further enhanced by increasing circuit performance. The amount of current that flows through the channel of a metal oxide semiconductor (MOS) transistor is directly proportional to a mobility of carriers in the channel, and the use of high mobility MOS transistors enables more current to flow and consequently faster circuit performance. For example, mobility of the carriers in the channel of a MOS transistor can be increased by producing a mechanical stress, i.e., strain, in the channel.
A number of approaches for inducing strain in Si- and Ge-containing materials have focused on exploiting the differences in the lattice constants between various crystalline materials. In one approach, thin layers of a particular crystalline material are deposited onto a different crystalline material in such a way that the deposited layer adopts the lattice constant of the underlying single crystal material.
Strain may also be introduced into single crystalline Si-containing materials by replacing Si in the lattice structure with a dopant, commonly referred to as substitutional doping. For example, substitution of germanium atoms for some of the silicon atoms in the lattice structure of single crystalline silicon produces a compressive strain in the resulting substitutionally doped single crystalline silicon material because the germanium atoms are larger than the silicon atoms that they replace. Alternatively, a tensile strain may be introduced into single crystalline silicon by substitutional doping with carbon, because carbon atoms are smaller than the silicon atoms that they replace. See, e.g., Judy L. Hoyt, “Substitutional Carbon Incorporation and Electronic Characterization of Si1-yCy/Si and Si1-x-yGexCy/Si Heterojunctions,” Chapter 3 in “Silicon-Germanium Carbon Alloy,” Taylor and Francis, N.Y., pp. 59-89, 2002, the disclosure of which is incorporated herein by reference.
In situ doping is often preferred over ex situ doping followed by annealing to incorporate the dopant into the lattice structure because the annealing may undesirably consume thermal budget. However, in practice in situ substitutional carbon doping is complicated by the tendency for the dopant to incorporate non-substitutionally during deposition, e.g., interstitially in domains or clusters within the silicon, rather than by substituting for silicon atoms in the lattice structure. See, e.g., the aforementioned article by Hoyt. Non-substitutional doping also complicates substitutional doping using other material systems, e.g., carbon doping of SiGe, doping of Si and SiGe with electrically active dopants, etc. As illustrated in FIG. 3.10 at page 73 of the aforementioned article by Hoyt, prior deposition methods have been used to make crystalline silicon having an in situ doped substitutional carbon content of up to 2.3 atomic %, which corresponds to a lattice spacing of over 5.4 Å and a tensile stress of less than 1.0 GPa. However, prior deposition methods are not known to have been successful for depositing single crystal silicon having an in situ doped substitutional carbon content of greater than 2.3 atomic %.
Therefore, there is a need to have a process for selectively and epitaxially depositing silicon and silicon-containing materials while accomplishing in situ substitutional doping of Si-containing materials. Desirably, such improved methods would be capable of achieving commercially significant levels of substitutional doping without unduly sacrificing deposition speed, selectivity, and/or the quality (e.g., crystal quality) of the deposited materials. Furthermore, the process should be versatile to form silicon-containing materials with varied elemental concentrations while having a fast deposition rate and maintaining a process temperature in the range of about 250° C.-550° C., and preferably about 500° C.-525° C. while maintaining a pressure of less than 200 Torr.